1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more specifically to a circuit device used to control the threshold value of MOSFETs formed on a semiconductor substrate.
2. Description of the Prior Art
In general, one of effective methods of reducing power consumption of a semiconductor integrated circuit device including MOSFETs is to reduce the supply voltage thereof, in the case of a CMOS integrated circuit in particular. In this method of reducing the supply voltage, however, the operation speed of the CMOS circuit is largely dependent upon the threshold value of the MOS transistors. For instance, when the supply voltage is 3.3V, even if the threshold value increases by 0.15V, the circuit speed is reduced by about 5%. However, when the supply voltage is 1V, the circuit speed is reduced as largely as twice.
Therefore, when not only the supply voltage but also the threshold value are reduced, it is possible to reduce the power consumption during operation, without reducing the circuit speed. When the threshold value is reduced, however, since the sub-threshold current of the MOSFET increases, this causes an increase of power consumption during standby. Therefore, it is desirable to increase the threshold value during standby but to decrease the same during operation.
Further, as described above, when only the supply voltage is reduced, since the dependence of the threshold value upon the circuit speed increases, the variation of the threshold value causes a large variation of the circuit speed. Therefore, it is desirable to reduce the variation of the threshold value during operation.
The threshold value of MOSFET can be modulated on the basis of the substrate potential (back-gate effect). Therefore, when a substrate bias voltage is applied (a potential lower than the source in NMOS but higher than the same in PMOS), threshold value can be increased. By utilizing this phenomenon, a technique of controlling the threshold value is disclosed by Document 1: K Seta, et al., "50% Active-Power Saving without Speed Degradation using Standby Power Reduction (SPR) Circuit", ISSCC Digest of Technical Papers, pp. 318-319, February 1996 or Document 2: T. Kobayashi, et al., "Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation" Proc. of CICC94, pp. 271-274, May, 1994, for instance.
In Document 1, a disclosed circuit is used to switch the threshold value between during standby and during operation. In Document 2, a disclosed circuit is used to compensate for the variation of the threshold during operation.
However, there has been not yet known a technique of realizing of both: a) to increase the threshold value during standby and to decrease the threshold value during operation and b) to reduce the variation of the threshold value during operation. In other words, in the circuit of Document 1, it is impossible to compensate for the variation of the threshold value during operation. In the circuit of Document 2, it is impossible to increase the threshold value during standby. Further, it is also impossible to combine the circuits of these two disclosed Documents 1 and 2 with each other simply. For instance, although the circuit disclosed by Document 2 can control the threshold value of N-channel MOSFETs (referred to as NMOSs simply, hereinafter) by reducing the potential of the P-type substrate below ground potential GND, the circuit disclosed by Document 1 fixes the potential of the P-type substrate at the ground GND.
Further, in the case of the circuit disclosed by Document 1, there exists another problem in that two supply voltages V.sub.PBB (=-2V) and V.sub.NBB (=4V) are required in addition to V.sub.DD (=2V) and GND (=0V).